Job type full-time
Full job description
At microchip, we work every day to innovate and develop products that solve our customers’ technology challengesOur team of more than 20,000 people worldwide is dedicated to delivering on the promise of working together to improve livesLearn about our guiding values that are the building blocks and foundation of our culture and discover how we make a positive impact in the communities in which we operateWe believe our culture fosters trust, collaboration and belongingOur people serve the industrial, computing, automotive, communications, aerospace and defense, and consumer market segmentsAs part of our global team, you can build technology solutions in our six growth areas – 5g, data centers, autonomous driving, the internet of things, electric vehicles, and artificial intelligence and machine learningAround the world, we are committed every day to recruiting, retaining and promoting people in our diverse workforceYour perspective, passion and ingenuity will contribute to achieving more as we fulfill our mission as a leading provider of smart, connected and secure embedded control solutionsJoin our community of exceptional people doing incredible thingsJob description: function: the design off asic blocks to be used within the next generation microchip soc fpga devicesThese asic blocks will contain riscv cpus and all the associated functions to create true soc functionalityIt is expected that the successful candidate will be able to customize and integrate third-party ip blocks, and to create custom blocks required for the soc integration and be involved from architecture through to production releaseIntegration also involves the design of compiled memories and integrating within the soc along with memory mbistThe candidate must be familiar with verilog coding for synthesis.
The position will involve interaction with the dublin based architecture and embedded software groups as well as the hyderabad india and us based logic verification and emulation groups.
Hands on experience with block level sta and full chip timing closure using primetime or tempus.
Experiencing in developing sta setup for primetime / tempus.
Good understanding of on-chip buses and bus structures (axi,amba, peripheral interconnects and communication protocols )
Verilog/ system verilog
Hands on with asic implementation flows including synthesis and sta.
Deep understanding least three of
Riscv or arm cpus
Network on chip bus interconnect (added plus point)
Pcie / usb
High speed serial interfaces
Io, mixed signal designs
Requirements/qualifications: at least 6 years of professional experience in digital design, synthesis, sta equivalent of bachelor of science engineering degree travel time:
Posted 30+ days ago