Job type full-time
Full job description
Physical design verification fill quality checks is the primary job functiongood understanding of fill qa concepts with handson on fill insertion along with runsets concept clarity is a mustdebug the drclvs rule deck failures during regressions and document the failures to the development teamunderstanding of calibre svrf is an additional requirement,good understanding of virtuoso and cadence skill scripting is requiredautomation of central regression system and maintainmanage test bench is the crucial job functionvalidating the fill runsets with after fill insertions and debugging the issues will be the work nature on daily basisExcellent exposure to analyse the fill drc issues for full chip and
B tech 6 yrs experience or ms 4 yrs in electrical electronic engineering is required experience with icv and calibre layout verification runsets along with tools like calibredrv background is a must experience working on 7nm or lower process nodes desired strong automationscripting skills are required tcl pythonperl desire to grow in the physical verification design career path is preferred
Inside this business group
As the world`s largest chip manufacturer, intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class supply chain and facilities supportEmployees in the technology development and manufacturing group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of moore’s law to bring smart, connected devices to every person on earth.
Work model for this role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned intel site and off-site.
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Posted 6 days ago