About blaize blaize leads new-generation computing unleashing the potential of ai to enable leaps in the value technology delivers to improve the way we all work and liveBlaize offers transformative edge computing solutions for ai data collection and processing at the edge of the network, with a focus on smart vision applications including automobility, retail, security, industrial, and metroBlaize has secured us$150m in equity funding to date from strategic and venture investors franklin templeton, denso, daimler, sparx group, magna, samsung catalyst fund, temasek, ggv capital, wavemaker, and sginnovateWith headquarters in el dorado hills (ca), blaize has teams in campbell (ca), cary (nc), and subsidiaries in hyderabad (india), manila (philippines), and leeds and kings langley (uk), with 300+ employees worldwideWww.blaize.com the edge ai and vision alliance announced blaize as the winner of the 2022 edge ai and vision product of the year – best edge ai processor – for the blaize® pathfinder p1600 embedded system on module (som)Https://www.blaize.com/press/best-edge-ai-processor/ roles and responsibilities we work on complex high performance, fully programmable, low-power design of graph streaming processor, an architecture specially designed for machine learning/visual applicationsAs a member of our focused group in hw engineering, the candidate will be involved in designing a stream processor and memory subsystem working on every aspect of hardware design and will be involved in close interactions with both sdk and backend teams for performance tuning, area, and power optimizations of multimillion gate designEducation and experience
Be/btech/me/mtech in computer science or electronics or electrical
3+ years of experience
Required knowledge, skills, and abilities
Capability to understand a given block specification and come up with microarchitecture
Capability to derive microarchitecture based on a given algorithm
Knowledge of computer architecture
Knowledge in digital logic for hw safety/protection – ecc, parity, wdt, etc.
Experience in multi-million gate asic design and verification methodologies
Experience in amba axi, ahb, and apb protocols
Knowledge of digital design methodologies and tool flow
Excellent logic design, debugging, and problem-solving skills.
Experience in logic design with verilog and/or system verilog and validation/verification
Experience in lint checks, synthesis, and timing analysis
Experience in multi-clock domain, interconnects
Knowledge of memory subsystem
Knowledge of automotive iso 26262 functional safety standard is a plus.
Experience with dsp, datapath design, and floating-point math a plus
Understanding of gpu/ai/ml processor architecture
Posted 30+ days ago